Department of Computer Science and Engineering

Indian Institute of Technology Hyderabad (IITH) is a premier institute of science and technology established in 2008. IITH has been consistently ranked in the&nbsp;<a href="https://iith.ac.in/reports/" rel="noopener noreferrer">top 10 institutes</a>&nbsp;in India for Engineering&nbsp;<a href="https://www.nirfindia.org/2021/EngineeringRanking.html" rel="noopener noreferrer" target="_blank">according to NIRF</a>&nbsp;making it one of the most coveted schools for science and technology in the country.

IITH offers&nbsp;<a href="https://iith.ac.in/academics/under-graduate/">undergraduate programs</a>&nbsp;in all the classical engineering disciplines, applied sciences, design, as well as several modern interdisciplinary areas. Students are given a flexibility to explore a broad set of areas, and potentially pursue a minor or double major in a discipline that is not their own. Students who wish to seek a deeper understanding of their own discipline are strongly encouraged to get involved in cutting-edge research with the help of a faculty to mentor them, and earn an Honors in their own field.

The very foundation of IIT Hyderabad is based on&nbsp;<a href="https://iith.ac.in/research/">research and innovation</a>. The vibrant research culture is evident from the number of patents and publications that IITH produces consistently every year. IITH offers&nbsp;<a href="https://iith.ac.in/academics/programmes-offered/">graduate programs</a>&nbsp;at both a masters, and a doctoral level, in several diverse areas. There are separate programs for technology, design, science, and liberal arts. The&nbsp;<a href="https://iith.ac.in/academics/post-graduate/">MTech program</a>&nbsp;is offered in various modes and durations to cater to the ever-growing need of postgraduate level professionals in the country.

IITH encourages and supports&nbsp;<a href="https://iic-iith.netlify.app/index.html" rel="noopener noreferrer" target="_blank">innovation and entrepreneurship</a>&nbsp;at every stage. The minor program in entrepreneurship is open to all students of IITH, and many of the courses are offered by industrialists who are entrepreneurs themselves. There are various&nbsp;<a href="https://iith.ac.in/research/centres-incubators/">innovation centers and incubators</a>&nbsp;that promote entrepreneurship and help mentor young innovators. IITH has been very successful in building tie-ups with leading academic institutions around the globe.

IITH enjoys a very special relationship with Japanese universities and industries that goes beyond academic and research collaborations. In fact, some of the iconic buildings in IITH campus will carry the signature of Japanese architecture.

IITH creates a unique holistic ecosystem for education that offers interactive learning, a very flexible academic structure, cutting-edge research, strong industry collaboration, and entrepreneurship. This is an environment which enables students and faculty to translate their dreams into realities.

IIT Hyderabad

The rise in mobile data traffic demands from indoor users (UEs) coupled with poor cellular coverage in indoor environments, triggering the growth of Femto cell deployments. However, due to densification of Femtos, frequency reuse one, and lack of coordination among Femtos in LTE HetNets, celledge users of Macro cells, who are in the vicinity of Femtos, get affected by cross-tier interference of the Femtos. In this work, we investigate how to improve performance of Victim Macro UEs (VMUEs). In order to provide better coordination between interfering Macro and Femtos, a centralized algorithm is proposed which performs Femto muting via joint Almost Blank Subframe (ABSF) and power control. During ABSF, Femto automatically adjusts its transmission power depending on the level of interference suffered by VMUEs. Our proposed scheme, called as RrMute, is compared with baseline schemes and the simulation results show that RrMute enhances the performance of VMUEs without jeopardizing the performance of Femto UEs in LTE HetNets. © 2017 IEEE.

World University root node

2017 23rd National Conference on Communications, NCC 2017

Enhancing performance of victim macro users via joint ABSF and dynamic power control in LTE HetNets

Representation and modelling of movements play a significant role in recognising actions in unconstrained videos. However, explicit segmentation and labelling of movements are non-trivial because of the variability associated with actors, camera viewpoints, duration etc. Therefore, we propose to train a GMM with a large number of components termed as a universal movement model (UMM). This UMM is trained using motion boundary histograms (MBH) which capture the motion trajectories associated with the movements across all possible actions. For a particular action video, the MAP adapted mean vectors of the UMM are concatenated to form a fixed dimensional representation referred to as 'super movement vector' (SMV). However, SMV is still high dimensional and hence, Baum-Welch statistics extracted from the UMM are used to arrive at a compact representation for each action video, which we refer to as an 'action-vector'. It is shown that even without the use of class labels, action-vectors provide a more discriminatory representation of action classes translating to a 8 % relative improvement in classification accuracy for action-vectors based on MBH features over naïve MBH features on the UCF101 dataset. Furthermore, action-vectors projected with LDA achieve 93% accuracy on the UCF101 dataset which rivals state-of-the-art deep learning techniques. © 2017 IEEE.

Department of Electrical Engineering

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Action-vectors: Unsupervised movement modeling for action recognition

Given a graph G and a pair (F1,F2) of graph families, the function GDISJG,F1,F2 takes as input, two induced subgraphs G1 and G2 of G, such that G1 ϵ F1 and G2 ϵ F2 and returns 1 if V (G1) / V (G2) = theta; and 0 otherwise. We study the communication complexity of this problem in the two-party model. In particular, we look at pairs of hereditary graph families. We show that the communication complexity of this function, when the two graph families are hereditary, is sublinear if and only if there are finitely many graphs in the intersection of these two families. Then, using concepts from parameterized complexity, we obtain nuanced upper bounds on the communication complexity of GDISJG,F1,F2 . A concept related to communication protocols is that of a (F1,F2)-separating family of a graph G. A collection F of subsets of V (G) is called a (F1,F2)-separating family for G, if for any two vertex disjoint induced subgraphs G1 ϵ F1,G2 ϵ F2, there is a set F ϵ F with V (G1)F and V (G2) / F = theta;. Given a graph G on n vertices, for any pair (F1,F2) of hereditary graph families with sublinear communication complexity for GDISJG,F1,F2 , we give an enumeration algorithm that finds a subexponential sized (F1,F2)-separating family. In fact, we give an enumeration algorithm that finds a 2o(k)nO(1) sized (F1,F2)-separating family; where k denotes the size of a minimum sized set S of vertices such that V (G) \ S has a bipartition (V1, V2) with G[V1] ϵ F1 and G[V2] ϵ F2. We exhibit a wide range of applications for these separating families, to obtain combinatorial bounds, enumeration algorithms as well as exact and FPT algorithms for several problems. © Sudeshna Kolay, Fahad Panolan, and Saket Saurabh; licensed under Creative Commons License CC-BY.

Leibniz International Proceedings in Informatics, LIPIcs

Communication complexity of pairs of graph families with applications

Given a bipartite graph (formula presented), a linear representation of the transversal matroid associated with G on the ground set U, can be constructed in randomized polynomial time. In fact one can get a linear representation deterministically in time (formula presented), where m=\vert U\vert and n=|V|, by looping through all the choices made in the randomized algorithm. Other important matroids for which one can obtain linear representation deterministically in time similar to the one for transversal matroids include gammoids and strict gammoids. Strict gammoids are duals of transversal matroids and gammoids are restrictions of strict gammoids. We give faster deterministic algorithms to construct linear representations of transversal matroids, gammoids and strict gammoids. All our algorithms run in time (formula presented), where m is the cardinality of the ground set and r is the rank of the matroid. In the language of parameterized complexity, we give an {XP} algorithm for finding linear representations of transversal matroids, gammoids and strict gammoids parameterized by the rank of the given matroid. © 2017, Springer International Publishing AG.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Linear representation of transversal matroids and gammoids parameterized by rank

A subfamily F' of a set family F is said to q-represent F if for every A s F and B of size q such that A n B = φ there exists a set A' s F' such that A' ∩ B = φ. Recently, we provided an algorithm that, for a given family F of sets of size p together with an integer q, efficiently computes a q-representative family F of F of size approximately (p+qp). In this article, we consider the efficient computation of q-representative families for product families F. A family F is a product family if there exist families A and B such that F = {A ∪ B: A ϵ A, B ϵ B, A n B = φ}. Our main technical contribution is an algorithm that, given A, B and q, computes a q-representative family F' of F. The running time of our algorithm is sublinear in ·F· for many choices of A, B, and q that occur naturally in several dynamic programming algorithms. We also give an algorithm for the computation of q-representative families for product families F in the more general setting where q-representation also involves independence in a matroid in addition to disjointness. This algorithm considerably outperforms the naive approach where one first computes F from A and B and then computes the q-representative family F' from F. We give two applications of our new algorithms for computing q-representative families for product families. The first is a 3.8408k no(1) deterministic algorithm for the Multilinear Monomial Detection (k-MlD) problem. The second is a significant improvement of deterministic dynamic programming algorithms for "connectivity problems" on graphs of bounded treewidth. © 2017 ACM.

ACM Transactions on Algorithms

Representative families of product families

Last Level Cache (LLC) plays an important role in increasing overall system performance of chip multiprocessor (CMP). The cores in a CMP has a private cache and a shared LLC whose size increases with each process generation. It has been observed that for different application on average 24% of the blocks are privately owned by the cores, and that the copies of these blocks in the LLC are redundant. This suggests that one needs to maintain only the tag portion of such private blocks in the LLC. Existing research has attempted to do this by partitioning the cache into tag-only and tag+data storage sections. This reduces the overall area of the LLC, but can degrade the performance to some extent. The tag-only storage stores the tags of the private blocks and if there are more such blocks in a set then these occupy the ways from the tag+data part. Thus, the chances of tag+data blocks staying in the cache reduces, affecting the performance. In this paper we propose to rectify the performance degradation by allowing more storage for the tag-only as well as tag+data parts. This is done by dynamically increasing the associativity of the sets. Experimental evaluation shows significant performance improvement with comparable area savings. © 2016 IEEE.

2016 20th International Symposium on VLSI Design and Test, VDAT 2016

Tag only storage for capacity optimised last level cache in chip multiprocessors

In multi-radio multi-channel (MRMC) WMNs, interference alleviation is affected through several network design techniques e.g., channel assignment (CA), link scheduling, routing etc., intelligent CA schemes being the most effective tool for interference mitigation. CA in WMNs is an NP-Hard problem, and makes optimality a desired yet elusive goal in real-time deployments which are characterized by fast transmission and channel switching times and minimal end-to-end latency. The trade-off between optimal performance and minimal response times is often achieved through CA schemes that employ heuristics to propose efficient solutions. WMN configuration and physical layout are also crucial factors which decide network performance, and it has been demonstrated in numerous research works that rectangular/square grid WMNs outperform random or unplanned WMN deployments in terms of network capacity, latency, and network resilience. In this work, we propose a smart heuristic approach to devise a near-optimal CA algorithm for grid WMNs (NOCAG). We demonstrate the efficacy of NOCAG by evaluating its performance against the minimal-interference CA generated through a rudimentary brute-force technique (BFCA), for the same WMN configuration. We assess its ability to mitigate interference both, theoretically (through interference estimation metrics) and experimentally (by running rigorous simulations in NS-3). We demonstrate that the performance of NOCAG is almost as good as the BFCA, at a minimal computational overhead of O(m) compared to the exponential of BFCA. © 2016 IEEE.

2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, ANTS 2016

Near optimal channel assignment for interference mitigation in wireless mesh networks

Abnormal activity recognition is a challenging task in surveillance videos. In this paper, we propose an approach for abnormal activity recognition based on graph formulation of video activities and graph kernel support vector machine. The interaction of the entities in a video is formulated as a graph of geometric relations among space–time interest points. The vertices of the graph are spatio-temporal interest points and an edge represents the relation between appearance and dynamics around the interest points. Once the activity is represented using a graph, then for classification of the activities into normal or abnormal classes, we use binary support vector machine with graph kernel. These graph kernels provide robustness to slight topological deformations in comparing two graphs, which may occur due to the presence of noise in data. We demonstrate the efficacy of the proposed method on the publicly available standard datasets viz. UCSDped1, UCSDped2 and UMN. Our experiments demonstrate high rate of recognition and outperform the state-of-the-art algorithms. © 2017 Elsevier Ltd

Pattern Recognition

Graph formulation of video activities for abnormal activity recognition

Service Chaining provides opportunities for network and service providers to implement their services and policies with finer granularity of an individual user or an application. However, the increasing number of Service Chains and middleboxes will introduce a larger number of flow rules and more consumption of Ternary Content Addressable Memory (TCAM), whose capacity is limited due to high cost and power consumption. This paper proposes to compress the flow rules for service chaining by optimizing the generation of Service Chain IDs that are widely used in packet tagging techniques for the Service Chaining. Our solution 1) makes service chain IDs aggregatable based on Common Forwarding Actions (CFAs) among the service chains, and 2) reduces the number of flow rules at each SDN switch to execute a larger number of forwarding actions for service chaining. The evaluation results showed that the proposed algorithm can reduce up to 76% of the flow rules using the randomly generated networks and service chains. Because the generation of Service Chain ID does not interfere the other flow rule compression techniques, our algorithm can also be used as a plug-in to the other Service Chaining mechanisms to optimize their ID generation. © 2016 IEEE.

2016 IEEE Conference on Network Function Virtualization and Software Defined Networks, NFV-SDN 2016

Optimizing Service Chain ID generation for flow rule compression

IP Mobility has many unresolved issues including triangle routing, session survivability, long delay and packet loss during hand-off. SDN-based IP Mobility promises to mitigate them by taking the advantage of network-wide visibility and centralized control. However, SDN-based approach still has some problems namely 1) large signaling overhead of controller and 2) high hand-off latency as the number of nodes and size of the network become large. This paper proposes a simple approach to efficiently handle IP mobility in SDN called 'FastSplit'. FastSplit reduces the signaling overhead to reestablish the new path after movement by reusing the existing path between correspondent node (CN) and mobile node (MN). Our solution is two fold: 1) it finds out the redirection/split point in polynomial time by restricting the search area along the previous path between MN and CN, and 2)using Sub-Optimality Factor (SOF) for determining the cost-effective split point in order to manage the trade-off between the optimality of reestablished path and the reduction of signaling overhead for handling host mobility. We present an algorithm to find out a split point between MN and CN so that the existing path configuration can be reused. The evaluation results showed that FastSplit contributes to achieving significantly less signaling cost by reducing the number of SDN switches to reconfigure, by up to 50% as well as shortening the hand-off duration by 17% in comparison to OpenFlow based Mobile IP. FastSplit is also proven that such performance can be achieved without compromising the overall end-to-end throughput between CN and MN at the new location. © 2016 IEEE.