Department of Computer Science and Engineering

Indian Institute of Technology Hyderabad (IITH) is a premier institute of science and technology established in 2008. IITH has been consistently ranked in the&nbsp;<a href="https://iith.ac.in/reports/" rel="noopener noreferrer">top 10 institutes</a>&nbsp;in India for Engineering&nbsp;<a href="https://www.nirfindia.org/2021/EngineeringRanking.html" rel="noopener noreferrer" target="_blank">according to NIRF</a>&nbsp;making it one of the most coveted schools for science and technology in the country.

IITH offers&nbsp;<a href="https://iith.ac.in/academics/under-graduate/">undergraduate programs</a>&nbsp;in all the classical engineering disciplines, applied sciences, design, as well as several modern interdisciplinary areas. Students are given a flexibility to explore a broad set of areas, and potentially pursue a minor or double major in a discipline that is not their own. Students who wish to seek a deeper understanding of their own discipline are strongly encouraged to get involved in cutting-edge research with the help of a faculty to mentor them, and earn an Honors in their own field.

The very foundation of IIT Hyderabad is based on&nbsp;<a href="https://iith.ac.in/research/">research and innovation</a>. The vibrant research culture is evident from the number of patents and publications that IITH produces consistently every year. IITH offers&nbsp;<a href="https://iith.ac.in/academics/programmes-offered/">graduate programs</a>&nbsp;at both a masters, and a doctoral level, in several diverse areas. There are separate programs for technology, design, science, and liberal arts. The&nbsp;<a href="https://iith.ac.in/academics/post-graduate/">MTech program</a>&nbsp;is offered in various modes and durations to cater to the ever-growing need of postgraduate level professionals in the country.

IITH encourages and supports&nbsp;<a href="https://iic-iith.netlify.app/index.html" rel="noopener noreferrer" target="_blank">innovation and entrepreneurship</a>&nbsp;at every stage. The minor program in entrepreneurship is open to all students of IITH, and many of the courses are offered by industrialists who are entrepreneurs themselves. There are various&nbsp;<a href="https://iith.ac.in/research/centres-incubators/">innovation centers and incubators</a>&nbsp;that promote entrepreneurship and help mentor young innovators. IITH has been very successful in building tie-ups with leading academic institutions around the globe.

IITH enjoys a very special relationship with Japanese universities and industries that goes beyond academic and research collaborations. In fact, some of the iconic buildings in IITH campus will carry the signature of Japanese architecture.

IITH creates a unique holistic ecosystem for education that offers interactive learning, a very flexible academic structure, cutting-edge research, strong industry collaboration, and entrepreneurship. This is an environment which enables students and faculty to translate their dreams into realities.

IIT Hyderabad

Count sketch [1] is one of the popular sketching algorithms widely used for frequency estimation in data streams, and pairwise inner product for real-valued vectors [2]. Recently, Shi et al. [3] extended the count sketch (CS) and suggested a higher-order count sketch (HCS) algorithm that compresses input tensors (or vectors) into succinct tensors which closely approximates the value of queried features of the input. The major advantage of HCS is that it is more space-efficient than count sketch. However, their paper didn't comment on estimating pairwise inner product from the sketch. This note demonstrates that HCS also closely approximates the pairwise inner product. We showed that their sketch gives an unbiased estimate of the pairwise inner product, and gives a concentration analysis of the estimate. © 2023 Elsevier B.V.

World University root node

Information Processing Letters

Unbiased estimation of inner product via higher order count sketch

We show that polynomial-size constant-rank linear decision trees (LDTs) can be converted to polynomial-size depth-2 threshold circuits LTF∘LTF. An intermediate construct is polynomial-size decision lists that query a conjunction of a constant number of linear threshold functions (LTFs); we show that these are equivalent to polynomial-size exact linear decision lists (ELDLs) i.e. decision lists querying exact threshold functions (ELTFs). © 2023 Elsevier B.V.

Linear threshold functions in decision lists, decision trees, and depth-2 circuits

Current advancements in the 5G network slicing admit a huge number of users avail a variety of services from the 5G Core network (5GC). While this is impressive, it opens the doors to security threats that could harm the smooth functioning of the 5GC as well as the legitimate users availing its services. This paper presents SENTINEL - a novel self protecting 5GC in the control plane by leveraging the Self Organizing Network (SON) paradigm. SENTINEL is fabricated as an autonomous framework, which protects itself in the control plane operations of 5GC from Distributed Denial of Service (DDoS) attack attempts by malicious users. Precisely, we build it as an Artificial Intelligence-based Hierarchical Temporal Memory (HTM) framework along with eXpress Data Path (XDP) and extended Berkeley Packet Filter (eBPF) based slice aggregator to aid in protecting the slice when the malicious users attempt a DDoS attack. While the attack is aimed at the 5GC control plane, the SENTINEL isolates the suspected malicious users with a sensitivity of '85.59%' from the 5GC. Thereby, it keeps the High Availability (HA) service for legitimate users intact, without incurring additional resources. © 2023 IEEE.

2023 15th International Conference on COMmunication Systems and NETworkS, COMSNETS 2023

SENTINEL: Self Protecting 5G Core Control Plane from DDoS Attacks for High Availability Service

Mobile operators are widely adopting Network Functions Virtualization (NFV) to get the benefits of virtualization, including ease of deployment, flexibility, and cost savings. NFV allows multiple virtualized Radio Access Networks (vRANs) to run on commodity hardware enabling joint signal processing and efficient interference management. In addition, mobile operators can run general-purpose workloads alongside vRANs to utilize spare system resources in the NFV infrastructure. In such a consolidated scenario, it is necessary to ensure that the Key Performance Indicators (KPIs) of vRAN workloads are always met. But the workload consolidation could cause high variability and unpredictability in the performance of the deployed vRANs due to contentions for shared system resources like CPU cores, Last Level Cache (LLC), etc. In order to address this problem, we present JARS - a joint allocation of radio and system resources for the NFV infrastructure - that dynamically adjusts system resources such as CPU cores and LLC-ways, and radio resources such as Physical Resource Blocks (PRBs) to ensure KPIs for vRANs and improve overall resource utilization by workload consolidation. We profile srsLTE to determine the minimal CPU core and LLC resource requirements to satisfy KPIs during different traffic loads, which is used in the JARS. Experimental studies on a prototype system show that the proposed JARS outperforms a state-of-the-art scheme by 23%. © 2023 IEEE.

Proceedings of IEEE/IFIP Network Operations and Management Symposium 2023, NOMS 2023

JARS: A Joint Allocation of Radio and System Resources for Virtualized Radio Access Networks

Airport surveillance activities using remote sensing images are challenging due to object variations largely affecting the geo-localization and object detection/segmentation tasks. Furthermore, the problem of localization is even larger due to scale variations. Traditionally image-based geo-referencing is accomplished by superimposing ground positioning system (GPS) location to the queried image. It is also observed both the query and the geo-tagged reference images are taken from the same ground view or aerial height in the case of remote sensing images. In our research, we intend to revisit the scale effect on object variability, by introducing the concept of geodesic representations along with image-matching networks. The architecture pipeline introduces a data processing layer wherein objects are geo-referenced to generate the metadata information. This metadata consists of three-dimensional data including the orientation information of the object. A regression task is added to the training set which leverages the metadata information. We use the gradient weighted class activation maps (Grad-CAM) to generate the activation maps and selection based on high threshold values for the pixel. The orientations and the locations are further calculated using the geodesic representations. The baseline architecture for local feature extraction uses a simple Siamese network with a ResNet backbone network. A NetVLAD layer is used to generate the global features. We also introduce a Geospatial attention network (GsAN) to aid in enhanced localization of objects. The dataset used for experiments consisted of CVUSA and our custom dataset providing airport runway views for different scales and arbitrary orientations. The performance evaluations focused on recall as a retrieval metric and comparing various loss functions. The performance metrics indicate a higher accuracy rate. © 2023 IEEE.

IEEE Aerospace Conference Proceedings

Geodesic Based Image Matching Network for the Multi-scale Ground to Aerial Geo-localization

In the midst of progressively shrinking silicon technologies, enhancements in performance and area requirements come at the cost of some side effects. One such cost is the deviation of nominal parameters of process, voltage, and temperature. Considered a manufacturing defect, variations limit the maximum achievable performance. These affected areas possess lower reliability and consume more power than their theoretical counterpart. In this paper, we study and mitigate variations observed in GDDRx based GPU memories. GPU devices are exploited primarily for their massive parallelism and applications with both regular and irregular memory accesses see significant performance benefits. We also find that these consume a significant portion of the total GPU power. We propose a variation mitigating and power-saving technique for GPU memories. This accounts for a power savings of up to 44.61% (20.3% on average). Simultaneously, we also maintain the device data which prevents page faults and re-computation costs. This, however, leads to some performance overheads, which are limited to 4%. Mitigation of process variation combined with state preservation leads to more reliable GPU computations. Additionally, our model lowers access latencies by 15.7% in comparison to a variation affected baseline GPU, which ultimately helps to improve the throughput of the device. © 2022 Elsevier B.V.

Microprocessors and Microsystems

Variation aware power management for GPU memories

Modelling uncertainty in deep learning is important for several high-risk applications such as autonomous driving and healthcare. Existing techniques for uncertainty modelling in deep learning such as Monte Carlo (MC) Dropout [1] and BatchEnsemble [2] suffer from some drawbacks. MC dropout shares parameters across models resulting in highly correlated predictions while BatchEnsemble requires storing additional parameters for each model in the ensemble. In our work, we aim to bring the best of both worlds by combining MC-dropout in the process of ensemble creation in BatchEnsemble. The proposed approach, Monte-Carlo BatchEnsemble, helps in generating ensembles with less correlation in prediction with the addition of a few parameters. The experimental results show the effectiveness of the proposed technique for image classification. © 2023 Owner/Author.

ACM International Conference Proceeding Series

Monte Carlo Dropout Based BatchEnsemble For Improving Uncertainty Estimation

Recent development of deep reinforcement learning models has impacted many fields, especially decision based control systems. Urban traffic signal control minimizes traffic congestion as well as overall traffic delay. In this work, we use a decentralized multi-agent reinforcement learning model represented by a novel state and reward function. In comparison to other single agent models reported in literature, this approach uses minimal data collection to control the traffic lights. Our model is assessed using traffic data that has been synthetically generated. Additionally, we compare the outcomes to those of existing models and employ the Monaco SUMO Traffic (MoST) Scenario to examine real-time traffic data. Finally, we use statistical model checking (specifically, the MultiVeStA) to check performance properties. Our model works well in all synthetic generated data and real time data. © 2023, IFIP International Federation for Information Processing.

IFIP Advances in Information and Communication Technology

Decentralized Multi Agent Deep Reinforcement Q-Learning for Intelligent Traffic Controller

In SDN-based networks, contextual understanding of network behaviour and safe execution of operational decisions are important as part of the network management process. Digital Twin Network (DTN) is a promising concept which creates a virtual twin of a live SDN-based network to monitor the network from different angles with various granularities and enables it to verify an operational change without disturbing the live one. However, modelling the arbitrary decisions by an SDN Controller to form a DTN and managing the contextual information in a DTN are challenging tasks in various aspects. This paper proposes a data representation based DTN architecture integrating Knowledge Graph (KG) for data modelling and storage and Template as the context description approach. The combination of KG and Template can make the DTN management scalable with the flexibility of defining the contextual information with the relationships between network entities. It also enables efficient querying of the data storage and provides the reusability of functions and data storage for the DTN applications development. The proposed DTN architecture was implemented using an ONOS-based SDN Controller and Neo4j-based KG with built-in DTN applications for practical use. The PoC implementation exhibited short query response time and high query throughput in reading from and updating a KG, though the initial creation of a KG incurs a considerable delay which increases with its size. © 2013 IEEE.

IEEE Access

Building a Digital Twin Network of SDN Using Knowledge Graphs

We aim to automate decades of research and experience in register allocation, leveraging machine learning. We tackle this problem by embedding a multi-agent reinforcement learning algorithm within LLVM, training it with the state of the art techniques. We formalize the constraints that precisely define the problem for a given instruction-set architecture, while ensuring that the generated code preserves semantic correctness. We also develop a gRPC based framework providing a modular and efficient compiler interface for training and inference. Our approach is architecture independent: we show experimental results targeting Intel x86 and ARM AArch64. Our results match or out-perform the heavily tuned, production-grade register allocators of LLVM. © 2023 Owner/Author.