Department of Computer Science and Engineering

Indian Institute of Technology Hyderabad (IITH) is a premier institute of science and technology established in 2008. IITH has been consistently ranked in the&nbsp;<a href="https://iith.ac.in/reports/" rel="noopener noreferrer">top 10 institutes</a>&nbsp;in India for Engineering&nbsp;<a href="https://www.nirfindia.org/2021/EngineeringRanking.html" rel="noopener noreferrer" target="_blank">according to NIRF</a>&nbsp;making it one of the most coveted schools for science and technology in the country.

IITH offers&nbsp;<a href="https://iith.ac.in/academics/under-graduate/">undergraduate programs</a>&nbsp;in all the classical engineering disciplines, applied sciences, design, as well as several modern interdisciplinary areas. Students are given a flexibility to explore a broad set of areas, and potentially pursue a minor or double major in a discipline that is not their own. Students who wish to seek a deeper understanding of their own discipline are strongly encouraged to get involved in cutting-edge research with the help of a faculty to mentor them, and earn an Honors in their own field.

The very foundation of IIT Hyderabad is based on&nbsp;<a href="https://iith.ac.in/research/">research and innovation</a>. The vibrant research culture is evident from the number of patents and publications that IITH produces consistently every year. IITH offers&nbsp;<a href="https://iith.ac.in/academics/programmes-offered/">graduate programs</a>&nbsp;at both a masters, and a doctoral level, in several diverse areas. There are separate programs for technology, design, science, and liberal arts. The&nbsp;<a href="https://iith.ac.in/academics/post-graduate/">MTech program</a>&nbsp;is offered in various modes and durations to cater to the ever-growing need of postgraduate level professionals in the country.

IITH encourages and supports&nbsp;<a href="https://iic-iith.netlify.app/index.html" rel="noopener noreferrer" target="_blank">innovation and entrepreneurship</a>&nbsp;at every stage. The minor program in entrepreneurship is open to all students of IITH, and many of the courses are offered by industrialists who are entrepreneurs themselves. There are various&nbsp;<a href="https://iith.ac.in/research/centres-incubators/">innovation centers and incubators</a>&nbsp;that promote entrepreneurship and help mentor young innovators. IITH has been very successful in building tie-ups with leading academic institutions around the globe.

IITH enjoys a very special relationship with Japanese universities and industries that goes beyond academic and research collaborations. In fact, some of the iconic buildings in IITH campus will carry the signature of Japanese architecture.

IITH creates a unique holistic ecosystem for education that offers interactive learning, a very flexible academic structure, cutting-edge research, strong industry collaboration, and entrepreneurship. This is an environment which enables students and faculty to translate their dreams into realities.

IIT Hyderabad

Regular monitoring is worthwhile to maintain a healthy crop. Historically, the manual observation was used to monitor crops, which is time-consuming and often costly. The recent boom in the development of Unmanned Aerial Vehicles (UAVs) has established a quick and easy way to monitor crops. UAVs can cover a wide area in a few minutes and obtain useful crop information with different sensors such as RGB, multispectral, hyperspectral cameras. Simultaneously, Convolutional Neural Networks (CNNs) have been effectively used for various vision-based agricultural monitoring activities, such as flower detection, fruit counting, and yield estimation. However, Convolutional Neural Network (CNN) requires a massive amount of labeled data for training, which is not always easy to obtain. Especially in agriculture, generating labeled datasets is time-consuming and exhaustive since interest objects are typically small in size and large in number. This paper proposes a novel method using k-means clustering with adaptive thresholding for detecting maize crop tassels to address these issues. The qualitative and quantitative analysis of the proposed method reveals that our method performs close to reference approaches and has an advantage over computational complexity. The proposed method detected and counted tassels with precision: 0.97438, recall: 0.88132, and F1 Score: 0.92412. In addition, using maize tassel detection from UAV images as the task in this paper, we propose a semi-automatic image annotation method to create labeled datasets of the maize crop easily. Based on the proposed method, the developed tool can be used in conjunction with a machine learning model to provide initial annotations for a given image, modified further by the user. Our tool's performance analysis reveals promising savings in annotation time, enabling the rapid production of maize crop labeled datasets. © 2021 Elsevier B.V.

World University root node

Department of Electrical Engineering

Remote Sensing Applications: Society and Environment

Efficient Maize Tassel-Detection Method using UAV based remote sensing

Recent trends of the use of deep neural networks (DNNs) in mission-critical applications have increased the threats of microarchitectural attacks on DNN models. Recently, researchers have proposed techniques for inferring the DNN model based on microarchitecture-level clues. However, existing techniques require prior knowledge of victim models, lack generality, or provide incomplete information of the victim model architecture. This paper proposes an attack that leaks the layer-type of DNNs using hardware performance monitoring counters (PMCs). Our attack works by profiling low-level hardware events and then analyzes this data using machine learning algorithms. We also apply techniques for removing the class imbalance in the PMC traces and for removing the noise. We present microarchitectural insights (hardware PMCs such as cache accesses/misses, branch instructions, and total instructions) that correlate with the characteristics of DNN layers. The extracted models are also helpful for crafting adversarial inputs. Our attack does not require any prior knowledge of the DNN architecture and still infers the layer-types of the DNN with high accuracy (above 90%). We have released the traces for public use at https://github.com/bhargavarch/DNN_RevEngg_PMC_Dataset. © 2021 ACM.

ACM International Conference Proceeding Series

Inferring DNN layer-types through a Hardware Performance Counters based Side Channel Attack

Generating succinct summaries (also known as sketches) of massive data streams is becoming increasingly important. Such a task typically requires fast, accurate, and small space algorithms in order to support the downstream applications, mainly in areas such as data analysis, machine learning and data mining. A fundamental and well-studied problem in this context is that of estimating the frequencies of the items appearing in a data stream. The Count-Min-Sketch Cormode and Muthukrishnan [2005] and Count-Sketch Charikar et al. [2004] are two known classical algorithms for this purpose. However, a limitation of these techniques is that the variance of their estimate tends to be large. In this work, we address this problem and suggest a technique that reduces the variance in their respective estimates, at the cost of little computational overhead. Our technique relies on the classical Control-Variate trick Lavenberg and Welch [1981] used for reducing variance in Monte-Carlo simulation. We present a theoretical analysis of our proposal by carefully choosing the control variates and complement them with experiments on synthetic as well as real-world datasets. © 2021 37th Conference on Uncertainty in Artificial Intelligence, UAI 2021. All Rights Reserved.

37th Conference on Uncertainty in Artificial Intelligence, UAI 2021

Variance Reduction in Frequency Estimators via Control Variates Method

Deep Neural Networks (DNNs) have revolutionized many aspects of our lives. The use of DNNs is becoming ubiquitous, including in software for image recognition, speech recognition, speech synthesis, language translation, to name a few. The training of DNN architectures, however, is computationally expensive. Once the model is created, its use in the intended application - the inference task, is computationally heavy too and the inference needs to be fast for real time use. For obtaining high performance today, the code of Deep Learning (DL) primitives optimized for specific architectures by expert programmers exposed via libraries is the norm. However, given the constant emergence of new DNN architectures, creating hand optimized code is expensive, slow and is not scalable. To address this performance-productivity challenge, in this article we present compiler algorithms to automatically generate high-performance implementations of DL primitives that closely match the performance of hand optimized libraries. We develop novel data reuse analysis algorithms using the polyhedral model to derive efficient execution schedules automatically. In addition, because most DL primitives use some variant of matrix multiplication at their core, we develop a flexible framework where it is possible to plug in library implementations of the same in lieu of a subset of the loops. We show that such a hybrid compiler plus a minimal library-use approach results in state-of-the-art performance. We develop compiler algorithms to also perform operator fusions that reduce data movement through the memory hierarchy of the computer system. Using Convolution Neural Network (CNN) models and matrix multiplication operations, we demonstrate that our approach automatically creates high performing DNN building blocks whose performance matches the performance of hand-crafted kernels of Intel's oneDNN library on high end CPUs. At the same time, our techniques take only a fraction of time (1/20 or less) compared to AutoTVM, a deep learning auto-tuner to create optimized implementations. © 2021 ACM.

ACM Transactions on Architecture and Code Optimization

PolyDL: Polyhedral Optimizations for Creation of High-performance DL Primitives

Neural ordinary differential equations (NODEs) treat computation of intermediate feature vectors as trajectories of ordinary differential equation parameterized by a neural network. In this paper, we propose a novel model, delay differential neural networks (DDNN), inspired by delay differential equations (DDEs). The proposed model considers the derivative of the hidden feature vector as a function of the current feature vector and past feature vectors (history) unlike only the current feature vector in the case of NODE. The function is modelled as a neural network and consequently, it leads to continuous depth alternatives to recent ResNet variants. For training DDNNs, we discuss a memory-efficient adjoint method for computing gradients and back-propagate through the network. DDNN improves the data efficiency of NODE by further reducing the number of parameters without affecting the generalization performance. Experiments conducted on real-world image classification datasets such as cifar10 and cifar100 to show the effectiveness of the proposed model. © 2021 ACM.

Delay differential neural networks

Fulltext

IEEE Communications Magazine

Guest Editorial: 5G for Verticals: From Theory to Practice and beyond

In a real-world setting, object instances from new classes can be continuously encountered by object detectors. When existing object detectors are applied to such scenarios, their performance on old classes deteriorates significantly. A few efforts have been reported to address this limitation, all of which apply variants of knowledge distillation to avoid catastrophic forgetting. We note that although distillation helps to retain previous learning, it obstructs fast adaptability to new tasks, which is a critical requirement for incremental learning. In this pursuit, we propose a meta-learning approach that learns to reshape model gradients, such that information across incremental tasks is optimally shared. This ensures a seamless information transfer via a meta-learned gradient preconditioning that minimizes forgetting and maximizes knowledge transfer. In comparison to existing meta-learning methods, our approach is task-agnostic, allows incremental addition of new-classes and scales to high-capacity models for object detection. We evaluate our approach on a variety of incremental learning settings defined on PASCAL-VOC and MS COCO datasets, where our approach performs favourably well against state-of-the-art methods. IEEE

IEEE Transactions on Pattern Analysis and Machine Intelligence

Incremental Object Detection via Meta-Learning

Dynamic Random Access Memory (DRAM) is the de-facto choice for main memories in modern day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic refreshing, usually at 64 ms, in order to ensure data persistence. Refreshing results in blocking of the memory device for performing normal read or write operations. However, it has been found that not all cells of the device requires uniform refreshing at 64 ms. Due to shrinking of technologies, deviations are observed in nominal parameters which causes variations in retention and restoration time. In this paper, we propose a retention aware DRAM refreshing model, which is operated in auto-refresh (AR) mode of a DRAM device. We call the proposed model Lightweight Retention Time Aware Refreshing, or simply LRAR, which can be operated either in a deterministic or an approximate mode while consuming a constant amount of hardware space. The former ensures consumption of least possible area in comparison to previously proposed works. While the latter is aimed to incorporate periodic refreshing for a newly emerged DRAM phenomenon called Variable Retention Time, or, VRT, which uses the basics of approximation. After extensive evaluation, we find that our proposed model reduces execution time of programs up to 11% (9.4% on average). The memory system's energy consumption is also reduced by an average of 11.5%, and refresh energy by an average of 73.6%. We achieve the aforementioned gains at a modest area overhead of 7$, 240 \mu \mathrm{m}^{2}\, (0.0018$% of a 400mm$^{2\, }$die) and storage overhead. © 2021 IEEE.

Proceedings - International Symposium on Quality Electronic Design, ISQED

Towards row sensitive dram refresh through retention awareness

Neuromorphic computing is a trending area in computer architecture which deals with the simulation of the brain on hardware. Machine learning problems are very complex to solve by simple computers that work based on Von-Neumann architecture so we need to find architectures that are inspired by the brain and efficient for machine learning, artificial intelligence, and more complex applications. The design has been proposed to implement the traditional software-based Spiking Neural Net-works (SNN) on hardware. However, a major challenge that this SNN based hardware face is the efficient on-chip communications between the neurons. Since SNN has lots of multicast messages to be communicated among the layers, traditional on-chip routing techniques are not sufficient. In this paper, we have proposed a dynamic clustering based on-chip routing mechanism for SNN based hardware. The clustering is based on the dynamic behavior of routers. Compared with the existing clustering-based on-chip routing technique, the proposed technique gives 14% to 38% improvement over average packet latency. © 2021 IEEE.

Proceedings - 2021 IEEE SmartWorld, Ubiquitous Intelligence and Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Internet of People, and Smart City Innovations, SmartWorld/ScalCom/UIC/ATC/IoP/SCI 2021

Efficient On-chip Communication for Neuromorphic Systems

An important idea in quantum networks is that of employing virtual edges or 'short-cuts' between quantum nodes. These edges, which are shared entangled pairs between two nodes that are not directly connected 'physically', are expected to reduce the average latency of entanglement distribution in quantum network routing. In this work, we show how to create such edges on an existing discrete event simulator for quantum networks called SeQUeNCe, and study the impact that these edges have on latency. Additionally, we implement a distributed routing algorithm on the simulator and demonstrate its use in conjunction with the virtual edges. We observe a reduction in latency when short-cuts are used, as is expected. Thus, with these modifications, we believe that SeQUeNCe (and other similar simulators) can be used for experimenting with advanced quantum networking protocols. © 2021 IEEE.