Department of Computer Science and Engineering

Indian Institute of Technology Hyderabad (IITH) is a premier institute of science and technology established in 2008. IITH has been consistently ranked in the&nbsp;<a href="https://iith.ac.in/reports/" rel="noopener noreferrer">top 10 institutes</a>&nbsp;in India for Engineering&nbsp;<a href="https://www.nirfindia.org/2021/EngineeringRanking.html" rel="noopener noreferrer" target="_blank">according to NIRF</a>&nbsp;making it one of the most coveted schools for science and technology in the country.

IITH offers&nbsp;<a href="https://iith.ac.in/academics/under-graduate/">undergraduate programs</a>&nbsp;in all the classical engineering disciplines, applied sciences, design, as well as several modern interdisciplinary areas. Students are given a flexibility to explore a broad set of areas, and potentially pursue a minor or double major in a discipline that is not their own. Students who wish to seek a deeper understanding of their own discipline are strongly encouraged to get involved in cutting-edge research with the help of a faculty to mentor them, and earn an Honors in their own field.

The very foundation of IIT Hyderabad is based on&nbsp;<a href="https://iith.ac.in/research/">research and innovation</a>. The vibrant research culture is evident from the number of patents and publications that IITH produces consistently every year. IITH offers&nbsp;<a href="https://iith.ac.in/academics/programmes-offered/">graduate programs</a>&nbsp;at both a masters, and a doctoral level, in several diverse areas. There are separate programs for technology, design, science, and liberal arts. The&nbsp;<a href="https://iith.ac.in/academics/post-graduate/">MTech program</a>&nbsp;is offered in various modes and durations to cater to the ever-growing need of postgraduate level professionals in the country.

IITH encourages and supports&nbsp;<a href="https://iic-iith.netlify.app/index.html" rel="noopener noreferrer" target="_blank">innovation and entrepreneurship</a>&nbsp;at every stage. The minor program in entrepreneurship is open to all students of IITH, and many of the courses are offered by industrialists who are entrepreneurs themselves. There are various&nbsp;<a href="https://iith.ac.in/research/centres-incubators/">innovation centers and incubators</a>&nbsp;that promote entrepreneurship and help mentor young innovators. IITH has been very successful in building tie-ups with leading academic institutions around the globe.

IITH enjoys a very special relationship with Japanese universities and industries that goes beyond academic and research collaborations. In fact, some of the iconic buildings in IITH campus will carry the signature of Japanese architecture.

IITH creates a unique holistic ecosystem for education that offers interactive learning, a very flexible academic structure, cutting-edge research, strong industry collaboration, and entrepreneurship. This is an environment which enables students and faculty to translate their dreams into realities.

IIT Hyderabad

A tighter coupling [1] between LTE and Wi-Fi interfaces can be achieved by integrating them at the radio protocol stack. LTE Wi-Fi radio level integration with IPsec tunnel (LWIP) is one such architecture introduced in Rel.13 of 3GPP. We have developed a variant of LWIP prototype and made commercial UE to readily work with the LWIP. The developed LWIP testbed uses OpenAirInterface (OAI) for LTE network and Cisco AP /Atheros device with Hostapd as Wi-Fi Access Point. In this demo, we present the aggregation benefits of using LWIP at flow/packet/bearer level steering across LTE and Wi-Fi links. © 2017 IEEE.

World University root node

2017 9th International Conference on Communication Systems and Networks, COMSNETS 2017

Tightly coupled LTE Wi-Fi radio access networks: A demo of LWIP

The notion of Total Interference Degree (TID) is traditionally used to estimate the intensity of prevalent interference in a Multi-Radio Multi-Channel Wireless Mesh Network (MRMC WMN). Numerous Channel Assignment (CA) approaches, link-scheduling algorithms and routing schemes have been proposed for WMNs which rely entirely on the concept of TID estimates. They focus on minimizing TID to create a minimal interference scenario for the network. In our prior works [1] and [2], we have questioned the efficacy of TID estimate and then proposed two reliable interference estimation metrics viz., Channel Distribution Across Links Cost (CDALcost) and Cumulative X-Link-Set Weight (CXLSwt) which are proven effective in both Grid and Random WMNS [3]. In this work, we assess the ability of these interference estimation metrics to replace TID as the interference-minimizing factor in a CA scheme implemented on a grid MRMC WMN. We carry out a comprehensive evaluation on ns-3 and then conclude from the results that the performance of the network increases by 10-15% when the CA scheme uses CXLSWt as the underlying Interference Mitigation Function (IMF) when compared with CA using TID as IMF. We also confirm that CDALcost is not a better IMF than TID and CXLSWt. © 2016 IEEE.

2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, ANTS 2016

Enhancing channel assignment performance in wireless mesh networks through interference mitigation functions

Exponential growth of mobile subscribers and various application data traffic requirements cause exorbitant load in Long Term Evolution (LTE) networks. Telecom operators are considering small cells and Wi-Fi for handling this huge traffic demand. As User Equipments (UEs) are typically associated with a near-by cell (eNB), spatio-temporal variation in traffic demands makes the LTE networks suffer from load imbalance problem. Due to the distributed nature of eNB operation in LTE Radio Access Network (RAN), traditional solutions to tackle load imbalance problem could lead to excessive overhead over X2 interface. Hence, managing densely deployed cells is very challenging in the existing distributed LTE RAN. In this work, load imbalance issue is addressed by proposing a centralized Software Defined LTE RAN (SD-LTE-RAN) framework and a novel QoS Aware Load Balance (QALB) algorithm. For taking load balance decisions, the QALB algorithm considers loads of neighbor cells, QoS profiles of UEs and their expected throughputs w.r.t. neighbor cells. Unlike existing load balance algorithms, it does not change handover-offset parameters of cells to avoid ping pong handovers. The proposed framework and QALB algorithm are implemented in NS-3 simulator. In various load balance scenarios, proposed QALB algorithm is able to maintain better QoS data rates (> 80% of their configured Guaranteed Bit Rates (GBRs)) for more than 70% of the cells in the network. While existing load balance algorithms are able to do the same for only 50% of the cells in the network. In overall, the QALB algorithm is able to decrease the total network overload by 15% compared to existing load balance algorithms. We also evaluated the QALB algorithm in mobility scenarios and identified that it is able to decrease average network overload by 10% compared to existing load balance algorithms. To evaluate the network wide fair load distribution, we defined load balance index (LBI) using Jain's Fairness Index. © 2016

Computer Communications

QoS Aware load balance in software defined LTE networks

A part-based approach for spontaneous expression recognition using audio-visual feature and deep convolution neural network (DCNN) is proposed. The ability of convolution neural network to handle variations in translation and scale is exploited for extracting visual features. The sub-regions, namely, eye and mouth parts extracted from the video faces are given as an input to the deep CNN (DCNN) inorder to extract convnet features. The audio features, namely, voice-report, voice intensity, and other prosodic features are used to obtain complementary information useful for classification. The confidence scores of the classifier trained on different facial parts and audio information are combined using different fusion rules for recognizing expressions. The effectiveness of the proposed approach is demonstrated on acted facial expression in wild (AFEW) dataset. © 2016 IEEE.

Proceedings - 2016 15th IEEE International Conference on Machine Learning and Applications, ICMLA 2016

Spontaneous facial expression recognition: A part based approach

This paper introduces a novel approach for generating videos called Synchronized Deep Recurrent Attentive Writer (Sync-DRAW). Sync-DRAW can also perform text-to-video generation which, to the best of our knowledge, makes it the first approach of its kind. It combines a Variational Autoencoder (VAE) with a Recurrent Attention Mechanism in a novel manner to create a temporally dependent sequence of frames that are gradually formed over time. The recurrent attention mechanism in Sync-DRAW attends to each individual frame of the video in sychronization, while the VAE learns a latent distribution for the entire video at the global level. Our experiments with Bouncing MNIST, KTH and UCF-101 suggest that Sync-DRAW is efficient in learning the spatial and temporal information of the videos and generates frames with high structural integrity, and can generate videos from simple captions on these datasets. © 2017 ACM.

MM 2017 - Proceedings of the 2017 ACM Multimedia Conference

Sync-DRAW: Automatic video generation using deep recurrent attentive architectures

Refactoring restructures a program to improve itsreadability and maintainability, without changing its originalbehavior. One of the key steps in refactoring is the identification ofpotential refactoring opportunities. In this paper, we discuss therelevance of two popular refactorings 'Replace Type Code withSubclass' and 'Replace Type Code with State' in real world Javaapplications and describe some of the challenges in automaticallyidentifying these refactoring opportunities. © 2017 IEEE.

Proceedings - 2017 IEEE/ACM 39th International Conference on Software Engineering Companion, ICSE-C 2017

Refactoring opportunities for replacing type code with state and subclass

We study polynomials computed by depth five Σ ∧ Σ ∧ Σ arithmetic circuits where ‘Σ’ and ‘∧’ represent gates that compute sum and power of their inputs respectively. Such circuits compute polynomials of the form (formula presented), where (formula presented) where ℓij are linear forms and ri, αi, t &gt; 0. These circuits are a natural generalization of the well known class of Σ ∧ Σ circuits and received significant attention recently. We prove an exponential lower bound for the monomial x1 · · · xn against depth five (formula presented) and (formula presented) arithmetic circuits where the bottom Σ gate is homogeneous. Our results show that the fan-in of the middle Σ gates, the degree of the bottom powering gates and the homogeneity at the bottom Σ gates play a crucial role in the computational power of Σ ∧ Σ ∧ Σ circuits. © Springer-Verlag GmbH Germany 2017.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

On Σ ∧ Σ ∧ Σ circuits: The role of middle Σ fan-in, homogeneity and bottom degree

Writing concurrent programs for shared memory multiprocessor systems is a nightmare. This hinders users to exploit the full potential of multiprocessors. STM (Software Transactional Memory) is a promising concurrent programming paradigm which addresses woes of programming for multiprocessor systems. In this paper, we implement BTO (Basic Timestamp Ordering), SGT (Serialization Graph Testing) and MVTO(Multi-Version Time-Stamp Ordering) concurrency control protocols and build an STM(Software Transactional Memory) library to evaluate the performance of these protocols. The deferred write approach is followed to implement the STM. A SET data structure is implemented using the transactions of our STM library. And this transactional SET is used as a test application to evaluate the STM. The performance of the protocols is rigorously compared against the linked-list module of the Synchrobench benchmark. Linked list module implements SET data structure using lazy-list, lock-free list, lock-coupling list and ESTM (Elastic Software Transactional Memory). Our analysis shows that for a number of threads greater than 60 and update rate 70%, BTO takes (17% to 29%) and (6% to 24%) less CPU time per thread when compared against lazy-list and lock-coupling list respectively. MVTO takes (13% to 24%) and (3% to 24%) less CPU time per thread when compared against lazy-list and lock-coupling list respectively. BTO and MVTO have similar per thread CPU time. BTO and MVTO outperform SGT by 9% to 36%. © 2017 IEEE.

2017 National Conference on Parallel Computing Technologies, PARCOMPTECH 2017

Performance comparison of various STM concurrency control protocols using synchrobench

We examine the applicability of Composite Items (CIs) for generating customized travel packages consisting of Points of Interest (POIs) in a given city. CIs have been shown to serve complex information needs such as selecting books for a reading club, identifying a set of products for a promotion, or planning a city tour. In the travel domain, a synthesized view of travel options in a city can be provided with a set of cohesive CIs, each of which is covering a different region in the city. In this paper, we attempt to understand the benefit of letting users customize travel packages, and examine the relationship between customization and personalization. For personalization, we gather user preferences on POI features when available or on latent topics extracted from POI tags. For customization, we develop a framework within which a user interacts with proposed travel packages and the system suggests new CIs according to refined user preferences. Our experiments reveal a tension between personalization and the cohesiveness of items forming each CI. As a result, customization is necessary to find a balance between POI personalization and CI cohesiveness. We also show that the refined user preferences obtained from customization in one city help build better travel packages in another city. © 2017 IEEE.

Proceedings - 2017 International Conference on Data Science and Advanced Analytics, DSAA 2017

Customizing travel packages with interactive composite items

Given a graph G, a non-negative integer k, and a weight function that maps each vertex in G to a positive real number, the Maximum Weighted Budgeted Independent Set (MWBIS) problem is about finding a maximum weighted independent set in G of cardinality at most k. A special case of MWBIS, when the weight assigned to each vertex is equal to its degree in G, is called the Maximum Independent Vertex Coverage (MIVC) problem. In other words, the MIVC problem is about finding an independent set of cardinality at most k with maximum coverage. Håstad in [Clique is hard to approximate within n[Formula Present]. Foundations of Computer Science, 1996.] showed that there is no [Formula Present] -factor approximation algorithm for the well-known Maximum Weighted Independent Set (MWIS) problem, where ϵ > 0, assuming NP-hard problems have no randomized polynomial time algorithms. Being a generalization of the MWIS problem, the above-mentioned inapproximability result applies to MWBIS too. Due to the existence of such inapproximability results for MWBIS in general graphs, in this paper, we restrict our study of MWBIS to the class of bipartite graphs. We show that, unlike MWIS, the MIVC (and thereby the MWBIS) problem in bipartite graphs is NPhard. Then, we show that the MWBIS problem admits an easy, greedy 1/2 -factor approximation algorithm in the class of bipartite graphs, which matches the integrality gap of a natural LP relaxation. This rules out the possibility of any LP-based algorithm that uses the natural LP relaxation to yield a better factor of approximation. © Springer International Publishing AG 2017.