Three Dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). In 3D IC using TSV, TSV noise coupling is one of the most significant consideration for circuit design. In this paper for the noise isolation between TSV and silicon substrate, p+ guard ring structure was proposed around signal TSV and examine with different doping concentration levels of the guard ring. In addition to that noise coupling from TSV to silicon substrate was analyzed with different liner (silicon dioxide, CVD diamond, Benzocyclobutene (BCB)) materials for the above structure. After investigating all results, TSV with BCB as liner material surrounded by p+ guard ring gives the better noise reduction from TSV to substrate by considering all constraints. © 2015 IEEE.