Rapid growth in semiconductor technology permits to integrate multiple number of processor cores with multi-level on-chip caches. Integration of more on-chip components increases the on-chip power density. As per recent studies, onchip caches are the principal contributors to the total power consumed by the chip. This cache power consumption can be divided into two major parts: dynamic power and static power. Dynamic power is consumed during cache accesses and static power is referred to as the leakage power of the cache. This increased power consumption increases effective chip-temperature which in turn increases the leakage power. In this paper we attempt to reduce the static power consumption by powering off cache ways from the cache banks of a Tiled DNUCA cache. We use a bank utilisation based criteria for the way shutdown decision. The number of ways to be turned off from a bank is chosen based on bank's usage statistics. The contents of the powered off cache ways are written back to main memory. Thus, depending upon the application's working set size and data distribution, a controlled number of ways from a set of banks can be dynamically shutdown to save leakage power dissipation. For a 4MB 8 way L2 Tiled DNUCA cache, experimental analysis shows 17% reduction in EDP and 33% reduction in the static power. The powered-off ways are also aligned, simplifying the gating circuitry. © 2016 ACM.