Performance of chip multiprocessors (CMPs) heavily depends on the efficiency of the caches. There is still a large gap between implemented replacement policies and the theoretical optimal policy. Among other factors, replacement policies play a major role in deciding the memory access time as they directly affect the miss-rate. In a CMP environment, the cost incurred by a miss in the higher level cache needs to take into account the communication latency over the on-chip network as well as power consumption.There are existing replacement policies which use this misscost rather than miss-count as an optimisation factor. These existing policies targeting the optimisation of miss-cost are mainly designed for the Last-Level Caches (LLC). Due to their significant hardware overheads, these policies are not directly applicable for the L1 caches. In this paper, we propose a new replacement policy, LA-LRU, for L1 caches which uses communication latency as a factor in deciding the victim. Experimental evaluation on full system simulation shows 7.4% improvement in Average Memory Access Time (AMAT) which leads to 7% improvement in Cycles Per Instruction (CPI). Reduction in on-chip communication also helps in improving the on-chip network power consumption by 14.8%. © 2017 IEEE.