This paper proposes a low complexity n-dimensional (nD) FastICA algorithm and architecture by introducing the concept of coordinate rotation where n ≥ 2. The proposed algorithm can merge the two key steps of conventional FastICA-preprocessing and update and is therefore capable of reducing the hardware complexity of the conventional FastICA significantly as demonstrated in this paper. Hardware implementation can further be simplified due to the recursive nature of the proposed algorithm where the same 2D hardware module can be used as the fundamental core to implement nD architecture. Together with the algorithm formulation, its functionality is also validated and hardware complexity is analyzed and compared with the conventional nD FastICA. © 2011 IEEE.