Through Silicon Via (TSV) is the major technology in order to transmit data among various devices in 3D IC. Therefore higher concentration of TSV is required for higher packing density in 3D IC. In order to obtain high density of TSV, the dimensions of TSV needs to be reduced. This may be achieved by increasing the surface area per layer which will benefit in packing of more components for any operation including logic implementation. In this paper we introduce electron spin rather than charge for the first time for interlayer signal transmission in 3D IC resulting in area efficiency. Ansys electromagnetic simulator (Maxwell 2D and 3D) and OOMMF simulation supported by theoretical analysis specifies an average of 90% area reduction per layer of 3D IC as compared to state-of-the art TSV. © 2017 IEEE.