The lifetime reliability of 3D-IC is limited due to defects, thermal issues and aging of Through-silicon-via (TSV). The state-of-The-Art methodologies for enhancing reliability are based on the fault tolerance techniques using redundant TSVs. The existing methodlogies do not consider the target lifetime, various failure mechanisms and workload. Thus the performance and cost of 3D-ICs is affected significantly. In this brief, we propose a TSV lifetime reliability aware 3D-IC framework with various TSV failure mechanisms and workload into consideration. Subsequently, validation and evaluation on IWLS'05 benchmark circuits is done for TSV lifetime reliability and compared with existing fault tolerance techniques to provide synergy between TSV count and targeted lifetime reliability of Router and Ring architectures. © 2004-2012 IEEE.