CNN involves large number of convolution of feature maps and kernels, necessary for extracting useful features for accurate classification. However, it requires significant amount of computationally intensive power and area hungry multiplications limiting its deployment on embedded devices under resource constrained scenario. To address this problem, we propose modified distributed arithmetic based low complexity multiplier-less CNN architecture design methodology. To the best of our knowledge, this is the first work of its kind where DA is modified and applied on CNN for realizing low complexity architecture implementation resulting power and area efficient design. Subsequently, the architecture is implemented and prototyped using Xilinx FPGA (Spartan 6) and synthesized on ASIC platform using Synopsys Design Compiler with TSMC 130nm technology library. The synthesis results and comparative analysis proved that the proposed modified DA based methodology implies less computations, complexity and up to 1.49x and 36.70x less area, 1.17x and 121.13x less power saving as compared to direct multiplication and multiplication with AND-OR based conventional methodologies respectively. © 2017 IEEE.