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Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs
, S. Agarwal, M. Bajaj, P.J. Oldiges, K.V.R.M. Murali, V.R. Rao
Published in Institute of Electrical and Electronics Engineers Inc.
2014
Volume: 61
   
Issue: 11
Pages: 3892 - 3895
Abstract
The metal-gate granularity-induced threshold voltage (VT) variability and (VT) mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode VT variability are analyzed. The VT mismatch study predicts lower mismatch figure of merit (AVT) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs. © 1963-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Electron Devices
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN00189383