In this paper, we propose an architecture design methodology for Discrete Hilbert Transform targeting the emerging real-time applications such as Cyber-Physical systems, Internet of Things and Remote Health Monitoring where the same chip-set needs to be used for various purposes under the resource constrained scenario. To arrive at a low complexity and reconfigurable architecture, the proposed architecture exploits the similarity in nature of computation which uses only a single core element recursively. The proposed architecture and state of art architecture are coded in VHDL for 16 bit word length and ASIC implementation has been done at UMC 90 nm technology @VDD = 1 V and @1 MHZ clock frequency. Comprehensive theoretical analysis, architecture implementation and experimental comparison results show that the proposed design saves 59.75%, 58.70% and 57.27% on chip area and 84.32%, 83.01% and 82.76% power consumption when compared to the state of the art method for N = 32, 64 and 128 respectively. Furthermore the proposed architecture works for N = 2m point irrespective of m being an odd or even integer, where the state of art architecture fails to perform form being odd integer. Copyright © 2018 American Scientific Publishers All rights reserved.