The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure. © 2022 IEEE.