Early stage power estimation is essential for hardware optimization but is challenging. In this paper, we propose GRILAPE, a graph representation inductive learning based average power estimation model using a novel graph attention-based mechanism that enables accurate, fast and transferable estimation of the average power of frontend ASIC RTL designs from RTL simulation without doing gate-level simulation. GRILAPE learns to propagate the toggle rates by replicating the logic computation procedure by embedding the feature values as vectors on each logic cell of the netlist file and estimating average power. We have achieved a mean improvement of 23.4% in average power estimation than the commercial RTL power estimation tool and 15.46X faster than the commercial gatelevel power estimation tool. We evaluate GRILAPE with state-of-the-art model GRANNITE to predict the output toggle rates for transferability and achieve better accuracy with a mean improvement of 14.36%. Our experimental results show the generalization and efficacy capability of GRILAPE. © 2023 IEEE.