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Fully integrated CMOS frequency synthesizer for ZigBee applicationsPublished in
2005
Pages: 780 - 783
A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18μ CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300μsec. Synthesizer consumes 22mW of power at supply voltage of 1.8V and occupies an active area of mm 2. © 2005 IEEE.
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About the journal
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
|---|---|
| ISSN | 10639667 |
Authors (1)
Ashudeb Dutta- A 2μW biomedical frontend with ΣΔ ADC for self-powered U-healthcare devices in 0.18μm CMOS technology
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