High mobility, electrolyte-gated FETs (EGFETs), based on precursor-derived oxide semiconductors, enable the possibility of achieving printed and low voltage (<2 V) operated circuits. These EGFETs can also be realized with displaced-gate geometries. However, the displaced-gate devices are typically slow due to high electrolyte resistance resulting from the large gate-channel distances. Here, we show that a thin insulating (composite solid polymer electrolyte) layer and a top-gate geometry can largely overcome this limitation, a comprehensive comparison between the displaced-gate and the top-gate devices has been provided. In order to facilitate circuit design, we have successfully developed accurate models to predict the behavior of these top-gate EGFETs. The importance of our modeling approach is further enhanced by the fact that appropriate predictive modeling strategies for printed circuits, especially for those that are based on oxide semiconductors, are largely missing. Unlike existing transistor models that do not cover all voltage regimes (below, near, and above threshold), we propose a new modeling methodology that matches very well with the measured data, is continuous and smooth over the entire voltage range, and can be easily incorporated into SPICE simulators. © 1963-2012 IEEE.