SiC MOSFETs are characterized by fast switching speeds typically in the range of 50-60 ns. However, the parasitic MOSFET capacitance and load parasitic capacitance form a resonant LC network with the layout parasitic inductance which causes unwanted overshoot and oscillations in the device voltage and current. This increases the losses in the converter and limits the maximum frequency of operation. Using an Active Gate Driver to reduce the ringing and oscillations definitely has its advantages and is widely reported in literature. However, in some of the AGD techniques the timing constraints on the controller are too restrictive and it is practically difficult to implement such fast control algorithms for a SiC MOSFET. This paper tries to address this issue by proposing an open loop AGD. The proposed method essentially sets the timing intervals of the stages apriori thereby eliminating the restrictive timing constraints on the controller.The proposed method has been tested on a two level VSI, switching at 100 kHz, running a 15 kW induction motor from a 400 V DC bus. The performance of the proposed technique as well as the operation are discussed in this paper. The test results reveal dominant dead time effects in the motor line current when the inverter is switching at 100 kHz, which generally are not observed in IGBT based drives where the IGBT switching frequency is less than 10 kHz. The reason for the dead time effects is investigated and appropriate compensation is carried out. © 2017 IEEE.