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Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact modelPublished in
2013
Pages: 146 - 150
A 65nm CMOS TEG for die-to-die and within-die variation analysis is reported. From measured Vth and Ion variation data of transistor pairs, die-to-die and within-die microscopic-parameter variations of a surface-potential model are extracted. Consideration of only five microscopic parameters is found sufficient to capture the channel-length dependence of these variations. © 2013 IEEE.
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About the journal
| Journal | IEEE International Conference on Microelectronic Test Structures |
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Authors (1)
Ashudeb Dutta- A 2μW biomedical frontend with ΣΔ ADC for self-powered U-healthcare devices in 0.18μm CMOS technology
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