With scaling FinFETs in advanced logic technologies, fin thickness, source/drain (S/D) regions doping and lattice hot-spot temperature predominantly affect the fin channel thermal conductivity due to enhanced phonon boundary scattering and phonon-dopant impurity (mass and size) fluctuations and leads to more device SHE. In this paper, we investigated these effects on silicon-on-insulator (SOI) fin field effect transistor (FinFET) electro-thermal performance by TCAD analysis considering Boltzmann transport equation (BTE) for phonons with relaxation time approximation. Results showed that the channel kth is reduced for $\mathrm{W}_{\text{Fin}} < 50\ \text{nm}$, doping $\mathrm{N} > 1\times 10^{19}\ \text{cm}-3$ and it is further degraded due to increasing local hot-spot temperature. However, Silicon-on-diamond (SOD) technology improves the device ET performance due to increase in heat energy flux through diamond (higher kth) BOX layer towards the substrate. Impact of within-chip ambient temperature $(\mathrm{T}_{\mathrm{A}})$ on device logic performance reveals that the SOD FinFET exhibits lower hot-spot temperature compared to conventional SOI FinFET. It is also revealed that with SOD technology, FinFETs can be aggressively scale down to sub-10nm node with better lattice heat mitigation, which improves the FinFET logic performance. © 2020 IEEE.