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DC compact model for SOI tunnel field-effect transistors
B. Bhushan, , V.R. Rao
Published in
2012
Volume: 59
   
Issue: 10
Pages: 2635 - 2642
Abstract
A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage V th, charge in the channel Q, gate capacitance C G, drain current I DS, subthreshold swing S, transconductance g m, and output conductance g DS, have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results. © 2012 IEEE.
About the journal
JournalIEEE Transactions on Electron Devices
ISSN00189383