In this brief, we propose a low-complexity design methodology to compute square-root and division using circular coordinate rotation digital computer (CORDIC). Unlike the state of the art methods, the proposed methodology eliminates the requirement of a separate hardware for square root and division computation in the CORDIC-based applications without compromising the computational speed, throughput and accuracy. The ASIC implementation of the proposed architecture has been performed using UMC 90 nm Technology node with 1.08 V @1 MHz and subsequently Xilinx Virtex-6 (XC6v1x240t)-based FPGA-prototyping has been done. The performance of the proposed methodology has been compared with the reported literature and significant power consumption improvement was observed without any additional area overhead. © 2004-2012 IEEE.