Time selective sampling is capable of eliminating strong interference signals without requiring a high linearity receiver front-end. This can be used to implement a full-duplex transceiver front-end by sampling the weak received signal at the zero-crossings of the strong transmitted signal. In this work, we propose a circuit technique to directly sample the received RF signal at the antenna port by exploiting implicit voltage-to-delay conversion occurring in a full-duplex system. The sampler is implemented in a 65 nm CMOS process, and simulation results show a sensitivity of -67 dBm in the presence of a +5.5 dBm Tx signal. The received signal has a 10 MHz bandwidth, and the overall receiver consumes 33.2 mW from a 1.2 V power supply. © 2018 IEEE.