The Incremental and iterative steps in the conventional digital IC design and automation flow increase the design time and non-recurring engineering cost (NRE), which are the two major driving factors of the IC industry. Reducing both at the same time is a challenge to the research community to come up with a design automation solution. In this paper, we propose a novel and unified methodology by merging the frontend and backend stages of the IC design process which eliminates the frontend CAD tool usage to minimize the Design time and NRE cost. Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in pre-computed technology libraries. We introduce the Dynamic Libraries, which store the layouts of the already designed blocks and their references for the later use in further designs. We further validated our methodology with 32-bit ALU which has its vital appearance in all the processors and controllers. The mapping techniques are validated on industrial standard benchmark circuits. These validations witness the considerable improvements in design time over the conventional design methodologies.