In the VLSI IC design, the number of incremental and iterative steps in the design automation methodology will decide the non-recurring-engineering (NRE) costs and time-to-market (TTM). Since these are the major driving factors of the IC design, many algorithms were proposed in the last few decades to minimize/optimize the number of design steps in the conventional VLSI IC Design methodology. However the frontend and backend designs have to be carried separately, which has limited the further minimization of the number of design steps. Here we propose a new unconventional design automation methodology, which reduces the NRE costs and TTM by merging the frontend and backend designs partially. It maps the input RTL description directly to their corresponding physical designs (derived using the existing CAD tools and stored in a pre-computed library) without any limitation on the Boolean function's input size. We have exploited the functional symmetry and negationpermutation- negation (NPN) class representations to decoct the library size and number of comparisons. The functional symmetry reduced the number of required pre-computed circuits in our experiments from 1031 to 222 (464.4% reduction in the memory size) and helps in maintaining the regularity in the design, which is a major concern for engineering change order. © 2014 IEEE.