Todays Electronic Design Automation industry is greatly affected by increased Non Recurring Engineering (NRE) costs and Time-to-Market (TTM) due to the incremental and iterative steps followed in the conventional digital IC design and automation flow. Reducing NRE cost and TTM at the same time is a daunting task to the research community without compromising on the performance. However, the complexity of hierarchical design steps can be reduced drastically by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs stored in pre-computed technology libraries. We use the Dynamic Libraries, which store the layouts of the already designed blocks and their references for the later use in further designs which reduces the design time and design cost significantly. Further we have exploited the functional symmetry and negation-permutation negation (NPN) class representations to decoct the library size and number of comparisons to further improvise on design time which results in reduced TTM. The functional symmetry reduced the number of required pre-computed circuits in our experiments from 1031 to 222 (464.4% reduction in the memory size). We further validated our methodology with adders and multiplier blocks which are the basic elements of any processor or controller. © 2014 IEEE.