This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude. © 2015 IEEE.

Ashudeb Dutta

Department of Electrical Engineering

P. Jha

P. Patra

Indian Institute of Technology Hyderabad (IITH) is a premier institute of science and technology established in 2008. IITH has been consistently ranked in the&nbsp;<a href="https://iith.ac.in/reports/" rel="noopener noreferrer">top 10 institutes</a>&nbsp;in India for Engineering&nbsp;<a href="https://www.nirfindia.org/2021/EngineeringRanking.html" rel="noopener noreferrer" target="_blank">according to NIRF</a>&nbsp;making it one of the most coveted schools for science and technology in the country.

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Journal	Data powered by TypesetAsia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Publisher	Data powered by TypesetIEEE Computer Society
ISSN	21592144