This article presents a power-efficient fully analog classifier architecture for the detection of critical cardiac abnormalities, i.e., asystole, extreme bradycardia, and tachycardia. To reduce power consumption and hardware complexity, an analog QRS complex detection circuit and arithmetic counter-based classification modules are introduced. The QRS detection circuit is autonomous and consumes an average current of 34 nA only, vis-à-vis state-of-the-art QRS detection designs that are digital signal processor (DSP) assisted and consume tens of microwatts of power. Furthermore, a heart-rate estimator provides the number of QRS complexes per minute. Each of the proposed modules is successfully validated through real electrocardiogram (ECG) test signals taken from the PhysioNet database. The proposed beat detector circuit exhibits a sensitivity of 97.85% and a positive prediction of 98.3%. Experimental results based on bedside monitor data show that the proposed classification module provides an overall sensitivity of 96.25% and a positive prediction of 96.97%. The complete classification architecture, implemented fully on analog platform, is simulated in the UMC 0.18- μm CMOS process and consumes 119-nW power with an active silicon area of 450×800μm. Moreover, the low-power implementation makes it suitable for long-term battery-operated remote ECG monitoring systems. © 1963-2012 IEEE.