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A Digital Frequency Multiplication Technique for Energy Efficient Transmitters
R.R. Manikandan, , B. Amrutur
Published in Institute of Electrical and Electronics Engineers Inc.
2015
Volume: 23
   
Issue: 4
Pages: 781 - 785
Abstract
A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-μm CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations. © 1993-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Very Large Scale Integration (VLSI) Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN10638210