This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single-well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of-110 dBc/Hz at 1 MHz offset. PLL consumes 450μW of power at 0.8 V supply with a settling time less than 25μs and core area is 705 μm × 510 μm at UMC 0.18 μm CMOS Mixed Mode Technology. PLL is successfully tested with the energy harvesting circuit. © 2016 IEEE.